This invention relates to memory devices and more particularly, to a memory cell for embedded memory applications. One particular application discussed herein is constructing content addressable memories (CAM""s) for use in embedded memory systems.
Semiconductor memory has continued to increase in density as a result of a number of technological advances in reducing transistor minimum feature sizes and increased flexibility in semiconductor device manufacturing, capabilities. Both static random access memories (SRAMs) as well as dynamic random access memories (DRAMs) have benefited from advances in commodity as well as embedded implementations. Embedded memory applications typically involve combining memory and other logic functions onto a single semiconductor device resulting, in very high bandwidth operation between the memory portion and the other circuitry. Common applications for embedded memory systems include microprocessor cache memory, microcontroller memory, and various system-on-a-chip applications.
In the networking industry, memory plays an important role in increasing the performance of networking systems in general, and specifically for example in the area of Layer 3 Fast Ethernet and Gigabit switches. One particular role which memory plays in such switches is for fast address look-ups. Typically, this type of operation involves comparing an incoming data packet""s address information with an existing database consisting of possible addresses indicating where the incoming packet can be forwarded. This type of operation is very well suited for implementation using Content Addressable Memory (CAM) especially as network protocols change and databases used for storing such information continue to grow.
Historically CAMs have not gained as widespread usage as DRAMs or SRAMs due to the larger cell size required to implement CAM. In application specific circuits (ASICs) however, CAMs have been often used to implement application specific memories for such applications as table look-up and associative computing.
For networking applications, CAM is best suited in applications that require the implementation of high performance wide word search algorithms. In such cases, CAM-based searches provide an advantage over other search algorithms implementations, such as software-implemented binary tree based searches for example. This is due to CAM""s capability of performing searches using very wide words and searching multiple locations in parallel. Typically, data in a CAM is accessed based on contents of its cells rather than on physical locations. A CAM operates by comparing information to be searched, referred to as search data, against the contents of the CAM. When (and if) a match is found, the match address is returned as the output.
A general background discussion about the various types of CAM cells and their operation is given in the article, xe2x80x9cContent-addressable memory core cellsxe2x80x94A survey.xe2x80x9d by Kenneth Schultz in INTEGRATION, the VLSI journal 23 (1997) pg. 171-188. As discussed in the article, CAM cells can be implemented with both SRAM and DRAM type memory cells. There are clearly advantages and disadvantages to using both types of memories to build CAMs. Generally, DRAM based CAMs have a higher density capacity due to the reduced number of elements required to build a cell as compared with SRAM based CAMs but suffer from the additional complication of requiring, periodic refresh in order to maintain the stored data. Various DRAM based CAM cells have been proposed such as in U.S. Pat. No. 3,701,980 to Mundy, and U.S. Pat. Nos. 4,831,585; 4,799,192 to Wade and Sodini and more recently to Lines et al. in U.S. application Ser. No. 09/533,128 assigned to MOSAID Technologies.
For example, a CMOS six transistor (6T) SRAM Cell has been widely used for many years, as shown schematically in FIG. 1. It is a simple robust arrangement and, depending on the ratio of the access transistors Ta and the inverter devices Tn and their complementary loads Tp, may be read either non-destructively or destructively, in which latter case, the data stored must be sensed and written back into the cell. Even the destructive read is a far simpler operation than the corresponding operation of a classic 1T cell DRAM. The drawback of this cell is that it requires a relatively large area for the six transistors and, now increasingly important in modern processes, their contacts and internal cross-coupled interconnections. The need for both complementary bit and {overscore (bit)} lines to each cell is a further constraint on packing density as is the need to supply voltages Vdd and Vss to each cell.
Also known for many years is the asymmetric 5T cell, as shown schematically in FIG. 2. This is a small improvement over the 6T cell of FIG. 1 but the added difficulty in ensuring reliable writing and the slower sensing on the single unbalanced bit line means that it is much less used.
Finally there are a number of versions of 4T cells. A common arrangement uses very high value resistors replacing the cross-coupled PMOS loads, as shown schematically in FIG. 3. These simply have to overcome the leakage of the cell storage nodes. The logic high level is also restored from the bit line each time the cell is accessed and the cell can thus operate in a dynamic mode.
Several attempts have also been made to make the access transistors serve much the same function as the resistive loads, feeding charge from the bit lines to maintain a xe2x80x9conexe2x80x9d level. In the mid 1970xe2x80x2s, Intel described a xe2x80x9cPlanar Refreshxe2x80x9d 1K DRAM using cells with four transistors with the word lines periodically pulsed to refresh all cells simultaneously. More recently, a four-transistor (4T) approach was presented by NEC, xe2x80x9cA 16 Mb 400 MHz Loadless CMOS Four-Transistor SRAM Macro,xe2x80x9d ISSCC, February, 2001 which used p-channel access transistors with higher leakage than their n-channel cross-coupled devices.
The above circuits have some disadvantages in that for many memory applications, there is an increased demand for single chip solutions or so called system-on-a-chip solutions, which require the merging of memory and logic functions onto a single semiconductor chip. For DRAM cells, the DRAM fabrication typically requires special processing steps to construct the cell capacitor structures, such as stacked or trench cell capacitors. Conversely, SRAM memory cells can be easily implemented by using standard logic processes or so-called xe2x80x9cnon-DRAM processesxe2x80x9d. A disadvantage however of SRAM memory, is that an SRAM cell typically comprised of 6T or 4T plus 2 resistors, takes up substantially more silicon area than a single transistor plus capacitor found in a typical DRAM cell. When used to construct ternary CAM (three logic state) memory cells, these characteristics of DRAM and SRAM cells are amplified due to the additional complexity required to implement the exclusive NOR function required of a typical ternary CAM cell resulting in relatively large CAM memory cells. And although DRAM based CAMs provide a density advantage over SRAM based CAMs, the special fabrication process steps typically required for DRAM based technology limit the current potential of DRAM based CAMs in embedded memory applications.
While processes offering DRAM process steps combined with regular logic capability are becoming more available, there is increasing concern that the complexity and cost justify their use only in a limited number of applications. More importantly, the time delay between the availability in the industry of such processes relative to simpler all-logic processes for a given geometry, further impacts the economic case for embedding DRAM. Thus for a given memory-to-logic ratio on a die, the die will actually be larger in the case of using a merged DRAM/logic 0.25 micron process to implement the memory portion vs. using SRAM on an all-logic 0.18 micron process to implement the memory portion. This is particularly problematic in applications such as CAM with a high logic overhead even in stand-alone form which incur an even greater area penalty when embedded.
As further considerations, portability between different foundry processes is poorer for the merged process and there are CAD tool inadequacies at this time.
Accordingly, primarily although not exclusively for embedded memory applications, it is desirable to provide a memory cell which benefits from DRAM based high density characteristics but can be implemented in a pure logic process, requiring no additional fabrication process steps for constructing capacitive structures. Preferably, this new cell consists of fewer transistors than typical SRAM memory cells and does not require a cell capacitor to store charge. It is further desirable to use this type of high density memory cell to construct embedded cells for CAM""s.
The present invention seeks to provide a memory cell for high density cell applications having a smaller cell size than conventional SRAM cells, and that is capable of static data storage that is, no refresh of data in the cell is required.
An advantage of the present invention is to replace both regular and embedded SRAM and DRAM cells. In particular, the memory cell can be built using a regular logic process with requiring additional process steps associated with complex capacitive structures. In addition, the memory cell is particularly well suited to complex functions requiring independent read and write paths and content-addressable memories (CAMs).
In accordance with this invention, there is provided a memory cell comprising:
(a) an CMOS inverting stage having an input node and an output node;
(b) an access transistor coupled between a bit line and the input node of said inverting stage for selectively coupling said bit line to said inverting stage input node in response to a control signal received along a control line; and
(c) a feedback element coupled between said inverting stage output node and a supply line for latching said inverting stage in a first logic state in response a signal at the input node of said inverting stage.